1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, to a semiconductor integrated circuit device which reduces leakage current by controlling a gate voltage in view of the temperature characteristics of the leakage current flowing when a field effect transistor is inactive.
2. Description of Related Art
In recent semiconductor integrated circuit devices, power consumption decreases along with decreasing power supply voltage while it increases at the same time along with increasing degree of integration and increasing access speed with the advent of the smaller geometry semiconductor process technology. Further, in recent semiconductor integrated circuit device, not only the power consumption during the active state but also the power consumption during the standby state pose a problem. An increase in the power consumption during the standby state is incurred by the smaller geometry semiconductor process technology and the lower power supply voltage particularly in a MISFET (Metal Insulator Semiconductor Field Effect Transistor). If the power supply voltage becomes lower, a threshold voltage of a field effect transistor should be lowered accordingly. The low threshold voltage causes an increase in subthreshold leakage current. Further, the smaller geometry semiconductor process technology causes a gate insulating layer to be thinner, which leads to an increase in leakage current.
The leakage current involves subthreshold current due to drift or diffusion of charges (subthreshold leakage current), junction leakage current between the drain region and the substrate region of MISFET (drain diffusion layer junction leakage), band to band tunnel leakage current between the drain region and the substrate region due to gate-drain electric field (GIDL: Gate Induced Drain Leakage), and tunnel leakage current between the gate and the drain, source and substrate regions. Among such leakage current, the subthreshold leakage current and the drain diffusion layer junction leakage current exhibit high temperature dependence. On the other hand, the GIDL and the tunnel leakage current between the gate and the drain, source and substrate regions exhibit low temperature dependence. In relation to such leakage current, “16.7-fA/Cell Tunnel-Leakage-Suppressed 16-Mb SRAM for Handling Cosmic-Ray-Induced Multierrors”, Kenichi Osada et al., IEEE journal of solid-state circuits, Vol. 38, No. 11, pp 1952-1957, NOVEMBER 2003 provides the description regarding the leakage current component and the relationship between the leakage current and the temperature by taking the leakage current during the standby state of a SRAM (Static Random Access Memory) cell as an example. Further, “Impact of Gate-Induced Drain Leakage on Retention Time Distribution of 256 Mbit DRAM With Negative Wordline Bias”, Michen Chang et al., IEEE Transactions On Electron Devices, Vol. 50, No. 4, pp 1036-1041, April 2003 provides, in FIG. 3, the description regarding the relationship between the number of fail bits and the word potential in a DRAM (Dynamic Random Access Memory) in reference to the gate voltage dependence of GIDL.
The leakage current which flows through a MISFET is described hereinafter with reference to FIG. 19. FIG. 19 shows the relationship between drain current and a gate voltage in a MISFET. In the graph of FIG. 19, the vertical axis indicates drain current in logarithmic scale, and the horizontal axis indicates a gate voltage in linear scale. As shown in FIG. 19, a certain amount of drain current flows through a MISFET in accordance with the voltage value of the gate voltage Vg when the gate voltage Vg exceeds a threshold.
The current which flows when the gate voltage Vg is below the threshold is called leakage current. When the gate voltage Vg is close to the threshold, the leakage current due to the drift of carriers is dominant. As the gate voltage Vg becomes lower, the leakage current due to the drift of carriers decreases and the leakage current due to the diffusion of carriers becomes dominant. The gate voltage at which the drain current is lowest is Vg(Id_min<ambient temperature>). At the gate voltage Vg(Id_min<ambient temperature>), drain diffusion layer junction leakage current flows. When the gate voltage falls below Vg(Id_min<ambient temperature>), GIDL increases.
The GIDL is described in further detail hereinafter. Due to the electric field between the drain region and the gate electrode, the electric field in the depletion layer in the vicinity of the surface between the drain region and the substrate region becomes stronger, and thereby the depletion layer which is created between the drain region and the substrate region is narrowed. This causes tunnel current, which is GIDL, to flow from the drain region to the substrate region. Accordingly, the GIDL becomes higher as a difference between the drain voltage and the gate voltage becomes larger.
The relationship between the drain current and the gate voltage of a MISFET is as indicated by the full line in FIG. 19 under ambient temperature, and as indicated by the dotted line under high temperature (e.g. 100° C.). Specifically, as the temperature of the substrate becomes higher, the subthreshold leakage current and the drain diffusion layer junction leakage increase, and thereby the minimum value of the leakage current increases. The voltage Vg(Id_min<high temperature>) at which the leakage current is minimal is lower than the voltage Vg(Id_min<ambient temperature>) under ambient temperature.
The increase in the leakage current raises the drawbacks such as an increase in the power consumption during standby of the semiconductor integrated circuit device and reduction of a data maintain period of a memory cell using a MISFET (e.g. DRAM cell).
An approach to reduce the subthreshold leakage current among the above leakage current is using an element such as a MTCMOS (Multi Threshold Complementary Metal Oxide Semiconductor) or a VTCMOS (Variable Threshold Complementary Metal Oxide Semiconductor).
Further, a technique of reducing the power consumption of an overall SRAM by controlling the source voltage of an NMOSFET in a SRAM cell is disclosed in “A 300 MHz 25 μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor”, Masanao Yamaoka et al., IEEE International Solid-State Circuits Conference, pp 494-495, 452, 2004. A technique of reducing the standby current in a DRAM by setting the gate voltage of an NMISFET in a memory cell to a negative voltage is disclosed in Japanese Unexamined Patent Application Publication No. 2000-11651. Further, a technique of reducing GIDL by setting the voltage applied to a word line during standby of a DRAM to be slightly higher than a ground voltage is disclosed in Japanese Unexamined Patent Application Publication No. 2003-173675.
Although the above techniques provide control of a gate voltage or a source voltage so as to reduce leakage current, they do not provide control in accordance with temperature. The gate voltage Vg(Id_min) at which the leakage current is minimal is temperature dependent. Therefore, although the above techniques can reduce leakage current when the semiconductor integrated circuit device is at an ambient temperature, for example, the leakage current undesirably increases when the temperature becomes higher.
Further, according to the technique disclosed in Japanese Unexamined Patent Application Publication No. 2000-11651 which sets the gate voltage to a negative voltage, the negative voltage can cause the drain current to increase to be non-minimal. Further, if an absolute value of the negative voltage of the gate voltage is large, much time and energy are required to increase the gate voltage to a power supply voltage. This hinders high-speed access to a memory cell, for example.